Energy converting device

ABSTRACT

Device for reversible conversion of electric power capable of being connected between at least an input alternating voltage source and at least a load forming an output alternating current source, each input alternating voltage source having a supply terminal and a neutral terminal. The device comprises at least a switching block and includes an input terminal for connecting the supply terminal, a single reference terminal and an output terminal. Each switching block consists of a switching matrix formed of capacitors and switching cells, individually controlled. Each reference terminal is connected to a reference point other than the neutral terminal, and each block comprises elements for permanently maintaining at a constant or null sign the difference of potential between the first input terminal and the reference terminal.

[0001] The present invention relates to a device for reversiblyconverting electrical energy with chopping between one or morealternating voltage sources and one or more alternating current sources.

[0002] Existing solutions based on contactors or thyristors andtransformers allow this type of conversion to be carried out.

[0003] However, these solutions allow only adjustment which is discreteand therefore imprecise, and the response thereof is slow.

[0004] These solutions further require transformers having-intermediatetaps in order to carry out the adjustment of the voltage. The cost ofthe assembly is therefore high.

[0005] Other solutions for producing energy converting devices useassociations of capacitors and switches allowing the current to becommutated between the various capacitors and the signal to be convertedin this manner.

[0006] Such use of commutated capacitors for carrying out a conversionof a signal is a conventional technique of electronics.

[0007] A semi-conductor network acting as switches and capacitorsarranged in the form of a matrix between a voltage source and a currentsource is used in the device described in French patent application No.00 06 786, filed on 26 May 2000, by the same applicant.

[0008] However, the device described in French patent application 00 06786 does not allow a conversion to be carried out between an alternatingvoltage source and an alternating current source.

[0009] A device which theoretically carries out a conversion between analternating voltage source and an alternating current source isdescribed in the article by D.-H. KWON, D.-D. MIN and J.-H.KIM, entitled“Novel topologies of AC choppers”, published in IEE Proceedings onElectr. Power Appl., pages 323-330, volume 143, No. 4, July 1996.

[0010] However, this article describes, in a purely theoretical manner,a specific case having three alternating current sources and disregardspractical installation problems relating to electronic circuits ofaverage and high power.

[0011] In particular, it will be appreciated that the electroniccircuits of this document pose excess-voltage risks which are high atlow power and critical at high power, in particular greater than 750 kW.

[0012] The object of the invention is to overcome this problem byallowing reversible conversion of electrical energy between one or morealternating voltage sources and one or more alternating current sources,which conversion is reliable for all power levels.

[0013] To this end, the invention relates to a device for reversiblyconverting electrical energy, which device can be connected between atleast one input alternating voltage source and at least one load whichforms an output alternating current source, each input alternatingvoltage source having a supply terminal and a neutral terminal, thedevice comprising at least one commutation block which is suitable forbeing associated with an output alternating current source and whichcomprises an input terminal, to which the supply terminal of the inputalternating voltage source can be connected, at least one referenceterminal and an output terminal, to which the load which forms theoutput alternating current source can be connected, the block alsocomprising a commutation matrix which is formed by capacitors andcommutation cells, which cells are controlled individually by means forcontrolling the operation thereof, characterised in that the or eachcommutation block comprises a single reference terminal which is at areference potential different from the potential of the neutral terminalof the source, and in that it comprises means for permanent maintenance,at a constant sign or zero, of the potential difference between theinput terminal and the reference terminal of the or each commutationblock.

[0014] According to other features:

[0015] the matrix of the or each block comprises at least one levelwhich comprises at least one row of commutation cells, which arearranged on the basis of a single commutation cell for each level of thesame row, each commutation cell being composed of two elements whichform a switch, the or each level defining two groups of switches whichare connected in series and the commutation matrix then defining twoextreme groups of switches, each commutation cell being associated witha capacitor which is sized in order to maintain, between the homologousterminals of the two switches of each commutation cell, a chargingvoltage which is equal to a fraction of the voltage of the inputalternating voltage source, which voltage fraction decreases as afunction of the row thereof starting from this source, the capacitors ofthe same row being connected in series between the two extreme groups ofswitches;

[0016] all of the switches of each commutation cell are unidirectionalin terms of voltage and bidirectional in terms of current;

[0017] all of the switches of each commutation cell are formed byelectronic components which are unidirectional in terms of voltage andunidirectional in terms of current;

[0018] all of the switches of each commutation cell are formed byelectronic components which are all identical, and in that each switchis constituted by identical elementary switches which are connected inseries and the number of which is a function of the maximum voltageapplicable between the terminals thereof;

[0019] it comprises means for monitoring the control means comprisingmeans for processing a reference signal in order to supply at the outputa plurality of secondary reference signals, and means for transmittingeach secondary reference signal to all of the control means of thecommutation cells of the same level of all of the matrices of all of theblocks of the device;

[0020] the processing means are suitable for supplying a plurality ofsecondary reference signals which are functions related by a portion ofthe reference signal, each secondary reference signal of a level havingat all times a value greater than or equal to the value of a secondaryreference signal of a level which is closer to the voltage source;

[0021] the monitoring means comprise means for generating asynchronisation signal in order to supply at the output a plurality ofsecondary synchronisation signals, and means for transmitting eachsecondary synchronisation signal to all of the control means of thecommutation cells of the same row of all of the matrices of all of theblocks of the device;

[0022] it comprises a single commutation block and can be connected to asingle input alternating voltage source, the neutral terminal of whichis accessible in order to allow a connection and which is associatedwith a single load which forms an output alternating current source, andin that it further comprises a first capacitor which can be connectedbetween the neutral terminal of the source and an output terminal of theload and a second capacitor which can be connected between the referenceterminal of the commutation block and the output terminal of the load;

[0023] it comprises a single commutation block and can be connected to asingle input alternating voltage source, the neutral terminal of whichis accessible in order to allow a connection and which is associatedwith a single load which forms an output alternating current source, andit comprises a shift block which comprises an input terminal which issuitable for being connected to the neutral terminal of the source, areference terminal which is connected to the reference terminal of thecommutation block and an output terminal which can be connected to theoutput terminal of the load, the shift block allowing the potential ofthe output terminal, which can be connected to an output terminal of theload, to be modified;

[0024] it comprises a first commutation block and a second commutationblock and can be connected to a single input alternating voltage source,the neutral terminal of which is accessible in order to allow aconnection and which is associated with a single load which forms anoutput alternating current source, the reference terminals of the twocommutation blocks being connected to each other, the first commutationblock being suitable for being connected at the input terminal thereofto the supply terminal of the source, the second commutation block beingsuitable for being connected at the input terminal thereof to theneutral terminal of the source, the device further being suitable forconnecting the load between the output terminals of the two commutationblocks;

[0025] the means for permanent maintenance, at a constant sign or zero,of the potential difference between the input terminal and the referenceterminal comprise inhibiting means which are associated with the or eachcommutation block and which comprise means for evaluating the sign ofthe potential difference between the input terminal and the neutralterminal of the source, which evaluation means are suitable forsupplying at the output a signal for inhibiting the commutation block,and the or each commutation block is suitable for connecting togetherthe input terminal, the reference terminal and the output terminalthereof when the inhibiting signal is received;

[0026] the inhibiting means are suitable for supplying the inhibitingsignal when the potential difference between the input terminal and theneutral terminal of the source is negative, the commutation matrixfurther being formed by electronic components which are orientated sothat the commutation block supports only a positive voltage or zerovoltage;

[0027] the inhibiting means are suitable for supplying the inhibitingsignal when the potential difference between the input terminal and theneutral terminal of the source is positive, the commutation matrixfurther being formed by electronic components which are orientated sothat the commutation block supports only a negative voltage or zerovoltage;

[0028] it can be connected to at least two input alternating voltagesources, the neutral terminals of which are all connected to each otherand which are associated with the same number of loads which form outputalternating current sources and output terminals of which are also allconnected to each other, and it comprises a plurality of commutationblocks, the reference terminals of the commutation blocks all beingconnected to each other;

[0029] the neutral terminals of the sources are accessible in order toallow a connection, and it comprises a shift block which comprises aninput terminal which is suitable for being connected to the neutralterminals, a reference terminal which is connected to all of thereference terminals of the commutation blocks and an output terminalwhich can be connected to all of the output terminals of the loads whichform an output alternating current source, the shift block allowing thepotential of the output terminal, which can be connected to the outputterminals of the loads, to be modified;

[0030] the means for permanent maintenance, at a constant sign or zero,of the potential difference between the input terminal and the referenceterminal comprise inhibiting means which are associated with the or eachcommutation block and which comprise means for comparing the potentialdifference between the input terminals and a terminal having a potentialcommon to all of the commutation blocks, such as the neutral terminalsof the sources, the output terminals of the loads or the referenceterminals, which means are suitable for supplying at the output signalsfor inhibiting the commutation blocks, and the or each commutation blockis suitable for connecting together the input terminal, the referenceterminal and the output terminal thereof when the inhibiting signal isreceived;

[0031] the inhibiting means are suitable for supplying an inhibitingsignal only to the block whose potential difference between the inputterminals and a terminal having a potential common to all of thecommutation blocks, such as the neutral terminals of the sources, theoutput terminals of the loads or the reference terminals, is theweakest, the commutation matrices further being formed by electroniccomponents which are orientated so that the blocks support only apositive voltage or zero voltage;

[0032] the inhibiting means are suitable for supplying an inhibitingsignal only to the block whose potential difference between the inputterminals and a terminal having a potential common to all of thecommutation blocks, such as the neutral terminals of the sources, theoutput terminals of the loads or the reference terminals, is thegreatest, the commutation matrices further being formed by electroniccomponents which are orientated so that the blocks support only anegative voltage or zero voltage;

[0033] it is suitable for being connected to three input alternatingvoltage sources which form the three phases of a three-phase electricalenergy supply network;

[0034] each matrix of each commutation block comprises a singlecapacitor and a single commutation cell.

[0035] The invention will be better understood from a reading of thedescription below which is given purely by way of example and withreference to the drawings, in which:

[0036]FIG. 1 is a schematic block diagram of a converting deviceaccording to the invention;

[0037]FIG. 2 is a schematic electrical diagram of a commutation block;

[0038]FIGS. 3, 4 and 5 are block diagrams, each illustrating in detailthe production of a device according to the invention, in the specificcase of connection to a single input alternating voltage source;

[0039]FIG. 6 is a block diagram illustrating in detail an energyconverting device according to the invention in the specific case ofthree input alternating voltage sources;

[0040]FIGS. 7 and 8 are schematic electrical diagrams of a commutationmatrix used in the invention when it comprises two levels and two rows,further illustrating in detail a control assembly of this device;

[0041]FIG. 9 is an illustration of the course of the reference signalsof the device described with reference to FIGS. 6 to 8;

[0042]FIG. 10 is an illustration of the course of the control signals ofthe device described with reference to FIGS. 6 to 8;

[0043]FIG. 11 is an illustration of the course of the voltage betweenthe input terminal and the reference terminal of a commutation block ofthe device described with reference to FIGS. 6 to 8;

[0044]FIG. 12 is an illustration of the course of the output voltages ofthe commutation blocks of the device described with reference to FIGS. 6to 8; and

[0045]FIG. 13 is an illustration of the course of the output currents ofthe commutation blocks of the device described with reference to FIGS. 6to 8.

[0046]FIG. 1 illustrates an energy converting device according to theinvention.

[0047] This device is connected to a plurality of input alternatingvoltage sources 1 ₁ to 1 _(n) which are constituted, for example, by thevarious phases of a multi-phase supply network.

[0048] The input alternating voltage sources 1 ₁ to 1 _(n) are all outof phase relative to each other. In this manner, if the system has ninput alternating voltage sources, they are out of phase relative toeach other by $\frac{2\pi}{n}.$

[0049] These input alternating voltage sources 1 ₁ to 1 _(n) eachcomprise a supply terminal 2 ₁ to 2 _(n) and a neutral terminal 3 ₁ to 3_(n), which neutral terminals 3 _(1 to 3) _(n) can be accessible or not.They are associated with loads 4 ₁ to 4 _(n) by means of commutationblocks 6 ₁ to 6 _(n) which are integrated in the energy convertingdevice. The loads 4 ₁ to 4 _(n) are bi-polar elements which areconstituted, for example, by resistors in series with inductors, and actas current sources. They each have an output terminal 5 ₁ to 5 _(n).

[0050] Each of the commutation blocks 6 ₁ to 6 _(n) comprises an inputterminal 7 ₁ to 7 _(n) which is connected to the supply terminal 2 ₁ to2 _(n) of the voltage source 1 ₁ to 1 _(n) which is associatedtherewith.

[0051] Each of the blocks 6 ₁ to 6 _(n) further comprises a singlereference terminal 9 ₁ to 9 _(n) and an output terminal 10 ₁ to 10 _(n).It also comprises a commutation matrix 12 ₁ to 12 _(n) and associatedinhibiting means 13 ₁ to 13 _(n) which are suitable for connectingtogether the input terminal 7 _(j), the reference terminal 9 _(j) andthe output terminal 10 _(j), of the block, thereby inhibiting the blockin question.

[0052] When the device comprises at least two input alternating voltagesources 1 ₁ to 1 _(n), each associated with a commutation block 6 ₁ to 6_(n), the neutral terminals 3 ₁ to 3 _(n) of the sources 1 ₁ to 1 _(n)are all connected together at the same potential.

[0053] For example, this potential is the neutral of the supply networkcorresponding to the input alternating voltage sources 1 ₁ to 1 _(n).

[0054] Furthermore, the reference terminals 9 ₁ to 9 _(n) of all of thecommutation blocks 6 ₁ to 6 _(n) are connected to each other andconstitute a common reference potential. The output terminals 5 ₁ to 5_(n) of the loads 4 ₁ to 4 _(n) are also all connected to each other atthe same potential.

[0055] Finally, the inhibiting means 13 ₁ to 13 _(n) comprise means forcomparing existing voltages between the input terminals 7 ₁ to 7 _(n)and a terminal having a common potential for all of the blocks 6 ₁ to 6_(n), such as the reference terminals 9 ₁ to 9 _(n) the output terminals5 ₁ to 5 _(n) or the neutral terminals 3 ₁ to 3 _(n).

[0056] In FIG. 1, as well as in the other Figures, the inhibiting means13 ₁ to 13 _(n) are illustrated delocalised at the commutation blocks 6₁ to 6 _(n). However, these circuits can also be grouped into a centralinhibiting circuit comprising single comparison means and controllingall of the blocks 6 ₁ to 6 _(n).

[0057] When the neutral terminals 3 ₁ to 3 _(n) are accessible, theconverting device advantageously comprises a shift block 14 whosearchitecture is identical to that of the commutation blocks, but withoutbeing associated with an input alternating voltage source.

[0058] The input terminal 15 is then connected to all of the neutralterminals 3 ₁ to 3 _(n) of the sources 1 ₁ to 1 _(n).

[0059] The shift block 14 also comprises a reference terminal 16 and anoutput terminal 17. It is constituted by a commutation matrix 18 whichis identical to the matrices 12 ₁ to 12 _(n) of the commutation blocks 6₁ to 6 _(n).

[0060] The reference terminal 16 is connected to the reference terminals9 ₁ to 9 _(n) of the commutation blocks 6 ₁ to 6 _(n) and the outputterminal 17 is connected to the output terminals 5 ₁ to 5 _(n) of theloads 4 ₁ to 4 _(n), as is described with reference to FIGS. 2, 7 and 8.

[0061] The shift block 14 allows the potential of the output terminals 5₁ to 5 _(n) of loads 4 ₁ to 4 _(n) to be shifted, as is described withreference to FIGS. 2, 7 and 8.

[0062] The converting device is thereby adapted to the type of the loads4 ₁ to 4 _(n).

[0063]FIG. 2 illustrates the architecture of a commutation matrix 12_(j), similar to those used in the invention.

[0064] The commutation block 6 _(j) comprises an input terminal 7 _(j),to which the supply terminal 2 _(j) of an alternating voltage source 1_(j), an output terminal 10 _(j) and a reference terminal 9 _(j) areconnected.

[0065] The commutation block 6 _(j) comprises a commutation matrix 12_(j) which is formed by capacitors 20 _(j,1,1) to 20 _(j,n,p) andcommutation cells 22 _(j,1,1) to 22 _(j,n,p).

[0066] Each commutation cell 22 _(j,i,k) is constituted by two switches24 _(j,i,k) and 26 _(j,i,k) and is connected, for the monitoringthereof, to control means 28 _(j,i,k) which are specific thereto.

[0067] In this device, the switches are unidirectional in terms ofvoltage and bidirectional in terms of current and the electroniccomponents which form the switches 24 _(j,i,k) and 26 _(j,i,k) of thecommutation cells 22 _(j,1,1) to 22 _(j,n,p) are unidirectional in termsof current and voltage, as is described with reference to FIG. 8.

[0068] The capacitors 20 _(j,i,k) and commutation cells 22 _(j,i,k)which form the matrix 12 _(j) as a whole are ordered in n levels 30_(j,1) to 30 _(j,n) and p rows 32 _(j,1) to 32 _(j,p).

[0069] Each matrix 12 _(j) optionally comprises a single level 30_(j,1,1) and a single row 32 _(j,1,1). In this case, the matrix 12 _(j)is constituted by a single commutation cell 22 _(j,1,1) and a singlecapacitor 20 _(j,1,1).

[0070] The n levels of the matrix 12 _(j) define n+1 groups of switches.

[0071] The first group of switches is constituted by theseries-connected circuit breakers 24 _(j,1,1) to 24 _(j,1,p) of the pcommutation cells of the first level. The (n+1)th group of switches isconstituted by the series-connected switches 26 _(j,n,1) to 26 _(j,n,p)of the p commutation cells of the nth level. The ith group of switches,with 1<i≦n, is constituted by the switches 24 _(j,i,1) to 24 _(j,i,p) ofthe p commutation cells of the ith level and the switches 26 _(j,i−1,1)to 26 _(i,i−1,p) of the p commutation cells of the (i−1)th level,alternately connected in series.

[0072] All of the groups of switches are connected at one of the endsthereof to the output terminal 10 _(j) of the commutation block 6 _(j).

[0073] The matrix 12 _(j) of the commutation block 6 _(j) furtherdefines two-extreme groups of switches. The first one is connected atone end to the output terminal 10 _(j) and at the other end to thereference terminal 9 _(j). The (n+1)th is connected at one end to theoutput terminal 10 _(j) and at the other end to the input terminal 7_(j).

[0074] Between two successive rows 32 _(j,k) and 32 _(j,k+1), ncapacitors of row k, 20 _(j,1,k) to 30 _(j,n,k), are connected in serieson the basis of one per level. In this manner, at the ith level, thecapacitor 20 _(j,i,k) is connected, on the one hand, to the ith group ofswitches and, on the other hand, to the (i+1)th group of switches.

[0075] Each capacitor 20 _(j,i,k) is suitable for maintaining betweenthe terminals thereof a charging voltage, being an increasing functionof row k thereof and representing a fraction of the partial voltage ofthe voltage source 1 _(j).

[0076] All of the commutation blocks 6 ₁ to 6 _(n) used in a convertingdevice according to the invention, as well as the shift block 14, areconstituted in the same manner as the commutation block 6 _(j) describedwith reference to FIG. 2.

[0077] In the same device, all of the commutation blocks 6 ₁ to 6 _(n)further comprise a matrix 12 ₁ to 12 _(n) which comprises the samenumber of levels and rows, and therefore the same number of commutationcells and capacitors.

[0078] The operation of such a device will now be explained.

[0079] Each of the commutation blocks 6 ₁ to 6 _(n) has two operatingmodes which are imposed by the inhibiting means 13 ₁ to 13 _(n).

[0080] In a first operating mode, a commutation block 6 _(j) convertsthe input signal into an output signal of the same type and having thesame frequency.

[0081] In this first operating mode, the commutation cells 22 _(j,i,k)of the commutation blocks 6 ₁ to 6 _(n) are controlled so as to maintainthe two switches of each cell in opposite states.

[0082] The voltage between the input terminal 7 _(j) and the referenceterminal 9 _(j) therefore has a constant sign. The sign thereof isdetermined by the orientation of the components in the matrix 12 _(j).

[0083] For example, a given orientation of the components, describedbelow with reference to FIG. 8, leads to a potential difference betweenthe input terminal 7 _(j) and the reference terminal 9 _(j) that isconstantly positive.

[0084] In this case, when the comparison means of the inhibiting means13 _(j) detect that the voltage between the input terminal 7 _(j) and aterminal having a potential common to all of the blocks 6 ₁ to 6 _(n),such as the neutral terminal 3 ₁ to 3 _(n), the output terminal 5 ₁ to 5_(n) or the reference terminal 9 ₁ to 9 _(n), is less than the voltagesbetween the input terminals of all of the other blocks of the system,and the same terminal having a common potential, the inhibiting means 13_(j) supply an inhibiting signal to the commutation block 6 _(j).

[0085] The commutation block then switches into a second operating mode,known as the “commutation block inhibition” mode, all of the switchesforming the commutation cells of a commutation block 6 _(j) are closed,thereby short-circuiting the input terminal 7 _(j), the referenceterminal 9 _(j) and the output terminal 10 _(j) of the commutation block6 _(j).

[0086] When the orientation of the components imposes a voltage betweenthe terminals 7 _(j) and 9 _(j) that is constantly negative during thecommutation phases, the inhibition criterion is inverted.

[0087] Owing to the inhibiting conditions of a commutation block whichare described above, there can be only one commutation block functioningat a time in the inhibition mode among all of the commutation blocks 6 ₁to 6 _(n) of the converting device.

[0088] If the device comprises a shift block, it functions in the samemanner as a non-inhibited commutation block.

[0089] The input alternating voltage sources 1 ₁ to 1 _(n) being out ofphase relative to each other, each of the commutation blocks 6 ₁ to 6_(n) switches to the inhibited mode for a period of $\frac{2\pi}{n}$

[0090] In such a device, placing all of the reference terminals 9 ₁ to 9_(n) and all of the neutral terminals 3 ₁ to 3 _(n) at the samepotential, the inhibiting periods controlled by the inhibiting means andthe orientation of the components ensure that the voltage between theinput terminal 7 ₁ to 7 _(n) and the reference terminal 9 ₁ to 9 _(n) ofeach of the commutation blocks is maintained at a constant sign or zero.

[0091] These voltages, referred to as Vb₁ to Vb_(n), respectively,remain directly linked with the source voltages 1 ₁ to 1 _(n) referredto as V1₁ to V1_(n).

[0092] It will be appreciated that, at all times, the relationshipVb₁−Vb₃=V1₁−V1₃ is verified. This relationship is verified for all ofthe blocks by circular permutation.

[0093] Similarly, the combined output voltages of the blocks referred toas V10₁-V10_(j) are also sinusoidal and generate in the loads 4 ₁ to 4_(n) sinusoidal currents which have the same frequency as the inputalternating voltage sources 1 ₁ to 1 _(n) and which are out of phaserelative to each other by $\frac{2\pi}{n}.$

[0094] In FIG. 3, the architecture of a device according to theinvention which is connected to a single input alternating voltagesource 1 is defined.

[0095] The device is connected to a load 4 which is associated with aninput alternating voltage source 1, the neutral terminal 3 of which isaccessible and comprises a commutation block 6.

[0096] The commutation block 6 comprises an input terminal 7 which isconnected to the supply terminal 2 of the input alternating voltagesource 1. It further comprises a reference terminal 9, an outputterminal 10 which is connected to the load 4 and a commutation matrix 12which is associated with inhibiting means 13.

[0097] In this configuration, the device further comprises a firstcapacitor 20 which is connected between the neutral terminal 3 of thesource 1 and the output terminal 5 of the load 4 and a second capacitor22 which is connected between the output terminal 5 of the load 4 andthe reference terminal 9 of the commutation block 6.

[0098] In this manner, a circuit is obtained which is suitable forconstantly maintaining a potential difference between the referencepoint 9 of the commutation block 6 and the neutral terminal 3 of theinput alternating voltage source 1.

[0099] In this configuration, the inhibiting means 13 of the commutationblock 6 further comprise means for evaluating the sign of the potentialdifference between the input terminal 7 and the neutral terminal 3,which corresponds to the potential difference at the source terminals 1.

[0100] When this voltage has a given sign, that is, for example,positive or zero, the block 6 functions as a commutation block. If thisvoltage has the opposite sign, negative in the example, the inhibitingmeans 13 control the commutation matrix 12 so that all of the switchesare closed, thereby short-circuiting the input terminal 7, the referenceterminal 9 and the output terminal 10, the block 6 then switches to theinhibited mode.

[0101] In order to reconstitute the integrity of a sinusoidal signal,the circuit must advantageously comprise means for shifting the signalof the input alternating voltage source 1 so that the input voltage isalways positive or zero.

[0102]FIG. 4 illustrates the case of a device according to the inventionwhich is connected to a single input alternating voltage source 2, theneutral terminal 3 of which is accessible, and which device comprises ashift block 14.

[0103] As has been described with reference to FIG. 3, the device isconnected to the input alternating voltage source 1, which is associatedwith the load 4 acting as a source of output current, and comprises thecommutation block 6.

[0104] The commutation block 6 comprises the matrix 12 which isassociated with the inhibiting means 13.

[0105] The device further comprises a shift block 14 which has an inputterminal 15 which is connected to the neutral terminal 3 of the source1, an output terminal 17 which is connected to the output terminal 5 ofthe load 4 and a reference terminal 16 which is connected to thereference terminal 9 of the commutation block 6.

[0106] The shift block 14 allows the potential of the output terminal 5of the load 4 to be modified, as is described with reference to FIGS. 2,7 and 8.

[0107]FIG. 5 illustrates a variant of the case of a device according tothe invention which is connected to a single input alternating voltagesource 1, the neutral terminal 3 of which is accessible.

[0108] When the device is connected to a single input alternatingvoltage source 1 whose supply terminal 2 and neutral terminal 3 areaccessible, this input alternating source 1 can be considered to beformed by two alternating sources 11 and 12 in phase-opposition.

[0109] The device therefore comprises two commutation blocks 6 ₁ and 6 ₂which are connected to the two virtual sources 1 ₁ and 1 ₂ inconventional manner, as has been described with reference to FIG. 1, theneutral terminal 3 acting as the supply terminal 2 ₂.

[0110] The commutation block 6 ₁ is associated with a load 4 ₁ and thecommutation block 6 ₂ is associated with a load 4 ₂. These two loads 4 ₁and 4 ₂ are connected to each other at the output terminals 5 ₁ and 5 ₂thereof.

[0111] Optionally, the two loads 4 ₁ and 4 ₂ can be replaced with asingle load 4 which is connected between the output points 10 ₁ and 10 ₂of the commutation blocks 6 ₁ and 6 ₂.

[0112] Such a device functions in the same manner as the general devicedescribed with reference to FIG. 1.

[0113] In such a physical configuration, however, it is not possible toconnect a shift block.

[0114] The operation of a device according to the invention is describedon the basis of the specific case described with reference to FIGS. 6 to8.

[0115]FIG. 6 illustrates a converting device according to the inventionin the specific case in-which it is connected to three input alternatingvoltage sources 1 ₁, 1 ₂ and 1 ₃ which are associated with three loads 4₁, 4 ₂ and 4 ₃ by means of commutation blocks 6 ₁, 6 ₂ and 6 ₃.

[0116] The three input alternating voltage sources 1 ₁, 1 ₂ and 1 ₃supply the same sinusoidal alternating signal of frequency f and arephase-shifted relative to each other by temporal spacing of$\frac{1}{3f}.$

[0117] . They each have a supply terminal 2 ₁, 2 ₂ and 2 ₃ and a neutralterminal 3 ₁, 3 ₂ and 3 ₃ which can be accessible or not.

[0118] For example, in the case of a three-phase supply network, each ofthe input alternating voltage sources represents a phase of the network.

[0119] Each commutation block 6 ₁, 6 ₂ and 6 ₃ comprises an inputterminal 7 ₁, 7 ₂ and 7 ₃, a reference terminal 9 ₁, 9 ₂ and 9 ₃ and anoutput terminal 10 ₁, 10 ₂ and 10 ₃. The input terminals 7 ₁, 7 ₂ and 7₃ are connected to the supply terminals 2 ₁, 2 ₂ and 2 ₃ and areindicated by the same references 7 ₁, 7 ₂ and 7 ₃.

[0120] They comprise commutation matrices 12 ₁, 12 ₂ and 12 ₃ which areassociated with inhibiting means 13 ₁, 13 ₂ and 13 ₃, respectively.

[0121] In a specific case, each commutation matrix 12 ₁, 12 ₂ and 12 ₃comprises only one level and only one row and therefore only onecommutation cell which is associated with a single capacitor.

[0122] As has been defined with reference to FIG. 1, the neutralterminals 3 ₁, 3 ₂ and 3 ₃ are all connected to each other and define aneutral which is common to the three input alternating voltage sources 1₁, 1 ₂ and 1 ₃.

[0123] The reference terminals 9 ₁, 9 ₂ and 9 ₃ are connected to eachother, as are the output terminals' 5 ₁, 5 ₂ and 5 ₃ of the loads 4 ₁, 4₂ and 4 ₃.

[0124] The details of the commutation block 6 ₁ and the control systemthereof are described with reference to FIGS. 7 and 8.

[0125] The matrix 12 ₁ of the block 6 ₁ comprises two levels 30 _(1,1)and 30 _(1,2) and two rows 32 _(1,1) and 32 _(1,2). Therefore, itcomprises four commutation cells 22 _(1,1,1), 22 _(1,1,2), 22 _(1,2,1)and 22 _(1,2,2) which are associated with the four capacitors 20_(1,1,1), 20 _(1,1,2), 20 _(1,2,1) and 20 _(1,2,2) and which arecontrolled by four control devices 28 _(1,1,), 28 _(1,1,2), 28 _(1,2,1)and 28 _(1,2,2), respectively.

[0126] The control system is constituted by a synchronisation module 34which comprises means 36 for generating symmetrical, alternating,triangular signals of frequency F as well as a delay circuit 38, whichproduce two signals Sd₁ and Sd₂ which are phase-shifted by a temporalspacing of $\frac{1}{2F}$

[0127] and which supply the control devices 28 _(1,1,1), 28 _(1,2,1) ofthe first row and 28 _(1,1,2), 28 _(1,2,2) of the second row,respectively.

[0128] Of course, if each commutation matrix comprises p rows, thetriangular signals which are emitted by the synchronisation module 34are all phase-shifted by a temporal spacing of $\frac{1}{pF}.$

[0129] These synchronisation signals are used by all of the commutationblocks of the device.

[0130] In the embodiment described here, frequency F is clearly greaterthan frequency f of the alternating voltage sources 1 ₁, 1 ₂ and 1 ₃ andis selected to represent more precisely a multiple of f for the sake ofsimplicity.

[0131] The device also comprises a monitoring signal generator 40 whichsupplies a continuous reference signal Sr which varies between 0 and 1and which corresponds to the adjustment of the quantity of energy to betransferred between the input alternating voltage source 6 ₁ and thecurrent source 4 ₁.

[0132] This reference signal Sr is processed at the output of themonitoring generator 40 by two processing modules 42 and 44 of the firstand second levels in order to provide at the output two secondaryreference signals Sr₁ and Sr₂, respectively. These two signals Sr₁ andSr₂ supply the control devices 28 _(1,1,1), 28 _(1,1,2) of the firstlevel and 28 _(1,2,1), 28 _(1,2,2) of the second level, respectively.

[0133] These secondary control signals are used by all of thecommutation blocks of the device.

[0134] The four control devices 28 _(1,1,1) to 28 _(1,2,2) aresynchronised and supply control signals at a frequency F, which signalsare suitable for ensuring, outside the inhibiting periods of the block 6₁, that the two switches of each cell are commutated to opposite states.

[0135] Each control device 28 _(1,1,1) to 28 _(1,2,2) comprises, forexample, a comparator whose logic state at the output is the result ofthe comparison of three signals, one of which is output by thesynchronisation module 34, another by the monitoring generator 40 and athird by the inhibiting means 13 ₁.

[0136] Therefore, the control device 27 _(1,i,k) supplies at the outputa control signal Sc_(1,i,k) whose value determines the state of thecommutation cell 22 _(1,i,k).

[0137] This control signal Sc_(1,i,k) must allow the three states of acommutation cell to be differentiated, that is to say, the two states ofopposite commutation of the switches and the inhibiting state, in whichthe two switches are closed.

[0138] An example of such a control system is described with referenceto FIG. 8.

[0139] In the embodiment described, it will be noted that the switchesof the extreme groups can support a voltage double that supported by theswitches of the intermediate group.

[0140] Advantageously, the switches 24 _(1,1,1), 24 _(1,2,1), 26_(1,1,2) and 26 _(1,2,2) of the extreme groups are formed by twoidentical elementary switches 50 which are arranged in series and whichare controlled in order to be in the same state at all times. Eachelementary switch 50 is formed by a transistor 52 which is arranged witha diode 54 in an anti-parallel state. In this manner, all of theelectronic components forming the switches of a commutation block areidentical.

[0141] Furthermore, all of the electronic components forming theelementary switches 50 of all of the commutation blocks of a deviceaccording to the invention are unidirectional in terms of current andvoltage. In the example described with reference to FIG. 8, the voltagebetween the input terminal 7 ₁ and the reference terminal 9 ₁ is alwayspositive or zero.

[0142] When all of the polarised electronic components of the device areinverted, this voltage is negative or zero.

[0143] A variant of the control system will now be explained in detailwith regard to the switches of a commutation cell, and more preciselythe commutation cell 22 _(1,2,2).

[0144] This cell comprises a first switch 24 _(1,2,2) which is formed bya single elementary switch 50 and a second switch 26 _(1,2,2) which isformed by two elementary switches 50. The cell is controlled by thecontrol device 28 _(1,2,2).

[0145] This control device 28 _(1,2,2) generates a control signalSc_(1,2,2) and is connected at the output directly to a first logic gateOR and, by means of an inverter, to a second logic gate OR.

[0146] The two gates OR are further connected to the inhibiting means 13₁ and receive signal In₁.

[0147] The first gate OR is connected at the output to the twoelementary switches which constitute the switch 26 _(1,2,2) in order tosupply the control signal Sc26 _(1,2,2) which is obtained for an ORlogic operation between the signals Sc_(1,2,2) and In₁. The second gateOR is connected at the output to the switch 24 _(1,2,2) in order tosupply the control signal Sc24 _(1,2,2) which is obtained by an OR logicoperation between the signals Sc_(1,2,2) and In₁.

[0148] Therefore, it will be appreciated that, when the inhibitingsignal In₁ equals zero, the control signals Sc24 _(1,2,2) and Sc26_(1,2,2) are complementary, which allows commutation to opposite statesto be ensured for the two switches which form the cell 22 _(1,2,2).

[0149] When the signal In₁ equals 1, the two control signals Sc24_(1,2,2) and Sc26 _(1,2,2) equal 1, which corresponds to the closing ofthe switches 24 _(1,2,2) and 26 _(1,2,2). The cell 22 _(1,2,2) is theninhibited.

[0150] The other cells of the device are controlled similarly.

[0151] In another example, the control signals are constituted by anumerical control encoded in two bits.

[0152] In this manner, when the inhibiting signal In₁ equals 0, thecontrol signal Sc_(1,i,k) equals 01 or 00. In the case in which it isequal to 01, the switch 24 _(1,i,k) of the commutation cell 21 _(1,i,k)is closed and the switch 26 _(1,i,k) of the same cell is open.Conversely, when the control signal Sc_(1,i,k) is equal to 00, theswitch 24 _(1,i,k) of the commutation cell 22 _(1,i,k) is open and theswitch 26 _(1,i,k) of the same cell is closed. Finally, if thecommutation block 6 ₁ is inhibited, inhibiting signal In₁ is equal to 1,signal Sc_(1,i,k) is equal to 11 or 10, and all of the switches of thecommutation cells 22 _(1,1,1) to 22 _(1,2,2) are closed.

[0153] When the device comprises a shift block, it is controlled in thesame manner as a commutation block in the absence of the inhibitingsignal. Therefore, all of the switches are controlled in opposedcommutations.

[0154] The simultaneous control of the two switches of the same cellwill not be further described below, being considered to be known in theprior art.

[0155] As will be appreciated with reference to FIG. 9, signal Sr₁intended for the control devices of the first level 30 _(1,1) is equalto 2×Sr between 0 and ½ and is fixed at 1 between ½ and 1. Signal Sr₂intended for the control devices of the second level 30 _(1,2) is equalto 0 up to ½, then 2×Sr between ½ and 1.

[0156] When the matrices 12 ₁ to 12 ₃ of the commutation blocks 6 ₁ to 6₃ comprise three levels, it is advantageous to determine three secondarycontrol signals. The first is equal to 3×Sr between 0 and ⅓, then beingfixed at 1, the second is equal to 0 before ⅓, 3×Sr between ⅓ and ⅔ and1 after ⅔, and the third is equal to 0 before ⅔ and 3×Sr between ⅔and 1. Generally, a device which comprises n level(s) has n signals Sr₁to Sr_(n).

[0157] For example, in the device described with reference to FIG. 6 to9, if signal Sr is equal to 0.25, signal Sr₁ equals 0.5 and signal Sr₂is zero.

[0158]FIG. 10 illustrates, on the one hand, the course of the threesignals Sr₁, Sd_(l) and In₁ which are provided at the input of thecontrol device 28 _(1,1,1) and, on the other hand, the course of thecontrol signal Sc26 _(1,1,1) which is provided by the control device 28_(1,1,1) to the switch 26 _(1,1,1) as a function of the signals receivedat the input.

[0159] The control signal Sc24 _(1,1,1) directed to the switch 24_(1,1,1) is not illustrated.

[0160] Signal Sd₁ is a triangular signal having an amplitude whichvaries between 0 and 1 and a frequency F which here is 20 f.

[0161] For the first row of the first level, when the inhibiting signalIn₁ is zero, signal Sc26 _(1,1,1) is a signal of rectangular wave formhaving a zero value when the relationship Sd₁>Sr₁ is verified and whichhas a value of one when the relationship Sd₁<Sr₁ is verified, as isillustrated with reference to FIG. 10.

[0162] This signal and signal Sc24 _(1,1,1) are complementary andproduce the commutation to opposite states of the switches of thecommutation cell 22 _(1,1,1).

[0163] When signal In₁ is equal to 1, signals Sc24 _(1,1,1) and Sc26_(1,1,1) are fixed at 1 and all of the switches of the commutation cell22 _(1,1,1) are closed.

[0164] All of the cells of the commutation matrix receive the sameinhibiting signal In₁, and therefore all of the switches are closed. Theblock is then in the inhibiting mode.

[0165] For the first row of the second level, in the example selectedwith Sr=0.25, signal Sr₂ is zero. In fact, when In₁ is zero, Sr₂ beingless than Sd₁, signal Sc_(1,2,1) is equal to zero. The commutation cell22 _(1,2,1) is in a fixed state, the switch 26 _(1,2,1) being open andthe switch 24 _(1,2,1) being closed.

[0166] When In₁ is equal to 1, the commutation block 6 is inhibited,signals Sc24 _(1,2,1) and Sc26 _(1,2,1) are fixed at 1 and all of theswitches are closed.

[0167] For the second row of the device, signal Sd₂ is a triangularsignal which has an amplitude which varies between 0 and 1 and afrequency F and which is phase-shifted by temporal spacing of$\frac{1}{2F}$

[0168] relative to signal Sd₁. Signals Sc_(1,1,2) and Sc_(1,2,2) arethen signals of rectangular wave form which are phase-shifted bytemporal spacing of $\frac{1}{2F}$

[0169] relative to signals Sc_(1,1,1) and Sc_(1,2,1).

[0170] Furthermore, inhibiting signal In₁ is common to all of the cellsof the block. Consequently, the various rows of the same level behave ina similar manner and have temporal spacing of $\frac{1}{2F}.$

[0171]FIG. 11 illustrates the input voltage of one of the commutationblocks of the device described with reference to FIG. 6 to 10.

[0172] Voltage Vb₁ corresponds to the potential difference between theinput terminal 7 ₁ of the commutation block 6 ₁ and the referenceterminal 9 ₁.

[0173] It will be appreciated that, although the voltage source 1 ₁associated with the block 6 ₁ is a sinusoidal alternating source,voltage Vb₁ has a particular shape because of the variations of thepotential of the reference terminal 9 ₁ and the inhibiting period of thecommutation block 6 ₁.

[0174] It has a positive portion with a double curve over a period of ⅔f and a zero portion over a period of ⅓ f corresponding to theinhibiting period of the block 6 ₁.

[0175] Voltages Vb₂ and Vb₃ have the same shape as voltage Vb₁, beingphase-shifted relative to each other by one-third of a period.

[0176] Each of the commutation blocks 6 ₁, 6 ₂ and 6 ₃ is inhibited forone-third of the period corresponding to frequency f of the inputalternating voltage sources 1 ₁, 1 ₂ and 1 ₃.

[0177] The three voltage sources 1 ₁, 1 ₂ and 1 ₃ are furtherphase-shifted relative to each other by one-third of a period.

[0178] The output voltages of the commutation blocks 6 ₁, 6 ₂ and 6 ₃are illustrated with reference to FIG. 12.

[0179] These output voltages Vs₁, Vs₂ and Vs₃ correspond to thepotential difference between the output terminals 10 ₁, 10 ₂ and 10 ₃ ofthe commutation blocks 6 ₁, 6 ₂ and 6 ₃ and the reference terminals 9 ₁,9 ₂ and 9 ₃ thereof.

[0180] They have an envelope corresponding to the general shape of inputvoltages Vb_(l), Vb₂ and Vb₃ which are modulated to frequency F of thecontrol means.

[0181] The illustration in FIG. 12 is symbolic and the ratio 20 betweenfrequencies f and F has not been complied with.

[0182] The charging currents which appear in the loads 4 ₁, 4 ₂ and 4 ₃are illustrated with reference to FIG. 13.

[0183] It will be appreciated that the charging currents 14 ₁, 14 ₂ and14 ₃ imposed by the combined voltages Vs₁-Vs₂, Vs₂-Vs₃ and Vs₃-Vs₁ aresinusoidal and have the same frequency f as the input alternatingvoltage sources 1 ₁, 1 ₂ and 1 ₃.

[0184] The strength of these currents is fixed in a continuous manner bycontrol signal Sr being determined.

[0185] It will clearly be appreciated that a device for convertingelectrical energy according to the invention has the advantage, owing tothe fact that the input voltage of the commutation blocks always has thesame sign or is zero, of being able to use electronic components whichare cheaper and of smaller dimensions than existing devices.

[0186] Furthermore, the electronic components used in the invention aresubjected to stresses in terms of voltage which are less great thanthose of existing devices.

[0187] Therefore, such a device can carry out a conversion of electricalenergy of average power or high power between one or more inputalternating voltage sources and one or more alternating current sources,using low-cost elements and with adjustment which is rapid, continuousand reliable.

[0188] Furthermore, conventional filters are arranged at each of theinput alternating voltage sources and at each of the output currentsources.

1. Device for reversibly converting electrical energy, which device canbe connected between at least one input alternating voltage source (1 ₁to 1 _(n)) and at least one load (4 ₁ to 4 _(n)) which forms an outputalternating current source (4 ₁₁ to 4 _(n)), each input alternatingvoltage source (1 ₁ to 1 _(n)) having a supply terminal (2 ₁ to 2 _(n))and a neutral terminal (3 ₁ to 3 _(n)), the device comprising at leastone commutation block (6 ₁ to 6 _(n)) which is suitable for beingassociated with an output alternating current source (4 ₁ to 4 _(n)) andwhich comprises an input terminal (4 ₁ to 7 _(n)), to which the supplyterminal (2 ₁ to 2 _(n)) of the input alternating voltage source (1 ₁ to1 _(n)) can be connected, at least one reference terminal (9 ₁ to 9_(n)) and an output terminal (10 ₁ to 10 _(n)), to which the load (4 ₁to 4 _(n)) which forms the output alternating current source can beconnected, the block (6 ₁ to 6 _(n)) also comprising a commutationmatrix (12 ₁ to 12 _(n)) which is formed by capacitors (20 _(j,i,k)) andcommutation cells (22 _(j,i,k)), which cells are controlled individuallyby means (28 _(j,i,k)) for controlling the operation thereof,characterised in that the or each commutation block (6 ₁ to 6 _(n))comprises a single reference terminal (9 ₁ to 9 _(n)) which is at areference potential different from the potential of the neutral terminal(3 ₁ to 3 _(n)) of the source (1 ₁ to 1 _(n)), and in that it comprisesmeans (13 ₁ to 13 _(n), 50) for permanent maintenance, at a constantsign or zero, of the potential difference between the input terminal (7₁ to 7 _(n)) and the reference terminal (9 ₁ to 9 _(n)) of the or eachcommutation block (6 ₁ to 6 _(n)).
 2. Converting device according toclaim 1, characterised in that the matrix (12 ₁ to 12 _(n)) of the oreach block (6 ₁ to 6 _(n)) comprises at least one level (30 _(j,1) to 30_(j,n)) which comprises at least one row (32 _(j,1) to 32 _(j,p)) ofcommutation cells (22 _(j,i,k)), which are arranged on the basis of asingle commutation cell (22 _(j,i,k)) for each level (32 _(j,1) to 32_(j,p)) of the same row (30 _(j,1) to 30 _(j,n)) each commutation cell(22 _(j,i,k)) being composed of two elements which form a switch (24_(j,i,k), 26 _(j,i,k)), the or each level (30 _(j,1) to 30 _(j,n))defining two groups of switches which are connected in series and thecommutation matrix (12 ₁ to 12 _(n)) then defining two extreme groups ofswitches, each commutation cell (22 _(j,i,k)) being associated with acapacitor (20 _(j,1,k)) which is sized in order to maintain, between thehomologous terminals of the two switches (24 _(j,i,k), 26 _(j,i,k)) ofeach commutation cell (22 _(j,i,k)), a charging voltage which is equalto a fraction of the voltage of the input alternating voltage source (1₁ to 1 _(n)), which voltage fraction decreases as a function of the rowthereof starting from this source, the capacitors (20 _(j,i,k)) of thesame row (32 _(j,1) to 32 _(j,p)) being connected in series between thetwo extreme groups of switches.
 3. Device according to claim 2,characterised in that all of the switches (24 _(j,i,k), 26 _(j,i,k)) ofeach commutation cell (22 _(j,i,k)) are unidirectional in terms ofvoltage and bidirectional in terms of current.
 4. Device according toclaim 3, characterised in that all of the switches (24 _(j,i,k), 26_(j,i,k)) of each commutation cell (22 _(j,i,k)) are formed byelectronic components (52, 54) which are unidirectional in terms ofvoltage and unidirectional in terms of current.
 5. Device according toclaim 2, characterised in that all of the switches (24 _(j,i,k), 26_(j,i,k)) of each commutation cell (22 _(j,i,k)) are formed byelectronic components (52, 54) which are all identical, and in that eachswitch is constituted by identical elementary switches (50) which areconnected in series and the number of which is a function of the maximumvoltage applicable between the terminals thereof.
 6. Device according toclaim 2, characterised in that it comprises means (34, 40, 42, 44) formonitoring the control means (28 _(j,i,k)) comprising means (42, 44) forprocessing a reference signal (Sr) in order to supply at the output aplurality of secondary reference signals (Sr₁ to Sr_(n)), and means fortransmitting each secondary reference signal to all of the control means(28 _(j,i,k)) of the commutation cells of the same level of all of thematrices (12 ₁ to 12 _(n)) of all of the blocks (6 ₁ to 6 _(n)) of thedevice.
 7. Device according to claim 6, characterised in that theprocessing means (42, 44) are suitable for supplying a plurality ofsecondary reference signals (Sr₁ to Sr_(n)) which are functions relatedby a portion of the reference signal (Sr), each secondary referencesignal (Sr₁ to Sr_(n)) of a level (30 _(j,k)) having at all times avalue greater than or equal to the value of a secondary reference signalof a level which is closer to the voltage source (1 ₁ to 1 _(n)). 8.Device according to claim 6, characterised in that the monitoring means(34, 40, 42, 44) comprise means for generating a synchronisation signal(34) in order to supply at the output a plurality of secondarysynchronisation signals (Sd₁ to Sd_(p)), and means for transmitting eachsecondary synchronisation signal (Sd₁ to Sd_(p)) to all of the controlmeans (28 _(j,i,k)) of the commutation cells of the same row of all ofthe matrices (12 ₁ to 12 _(n)) of all of the blocks (6 ₁ to 6 _(n)) ofthe device.
 9. Device according to claim 1, characterised in that itcomprises a single commutation block (6) and can be connected to asingle input alternating voltage source (1), the neutral terminal (3) ofwhich is accessible in order to allow a connection and which isassociated with a single load (4) which forms an output alternatingcurrent source, and in that it further comprises a first capacitor (20)which can be connected between the neutral terminal (3) of the source(1) and an output terminal (5) of the load (4) and a second capacitor(22) which can be connected between the reference terminal (9) of thecommutation block (6) and the output terminal (5) of the load (4). 10.Device according to claim 1, characterised in that it comprises a singlecommutation block (6) and can be connected to a single input alternatingvoltage source (1), the neutral terminal (3) of which is accessible inorder to allow a connection and which is associated with a single load(4) which forms an output alternating current source, and in that itcomprises a shift block (14) which comprises an input terminal (15)which is suitable for being connected to the neutral terminal (3) of thesource (1), a reference terminal (16) which is connected to thereference terminal (9) of the commutation block (6) and an outputterminal (17) which can be connected to the output terminal (5) of theload (4), the shift block (14) allowing the potential of the outputterminal (17), which can be connected to an output terminal (5) of theload (4), to be modified.
 11. Device according to claim 1, characterisedin that it comprises a first commutation block (6 ₁) and a secondcommutation block (6 ₂) and can be connected to a single inputalternating voltage source (1), the neutral terminal (3) of which isaccessible in order to allow a connection and which is associated with asingle load (4) which forms an output alternating current source, thereference terminals of the two commutation blocks (6 ₁, 6 ₂) beingconnected to each other, the first commutation block (6 ₁) beingsuitable for being connected at the input terminal (7 ₁) thereof to thesupply terminal (2) of the source (1), the second commutation block (6₂) being suitable for being connected at the input terminal (7 ₂)thereof to the neutral terminal (3) of the source (1), the devicefurther being suitable for connecting the load (4) between the outputterminals (10 ₁, 10 ₂) of the two commutation blocks.
 12. Deviceaccording to claim 9, characterised in that the means for permanentmaintenance, at a constant sign or zero, of the potential differencebetween the input terminal (7; 7 ₁, 7 ₂) and the reference terminal (9;9 ₁, 9 ₂) comprise inhibiting means (13; 13 ₁, 13 ₂) which areassociated with the or each commutation block (6; 6 ₁, 6 ₂) and whichcomprise means for evaluating the sign of the potential differencebetween the input terminal (7) and the neutral terminal (3) of thesource (1), which evaluation means are suitable for supplying at theoutput a signal for inhibiting the commutation block (6), and in thatthe or each commutation block (6; 6 ₁, 6 ₂) is suitable for connectingtogether the input terminal (7; 7 ₁, 7 ₂), the reference terminal (9; 9₁, 9 ₂) and the output terminal (10; 10 ₁, 10 ₂) thereof when theinhibiting signal is received.
 13. Device according to claim 12,characterised in that the inhibiting means (13) are suitable forsupplying the inhibiting signal when the potential difference betweenthe input terminal (7) and the neutral terminal (3) of the source (1) isnegative, the commutation matrix (12) further being formed by electroniccomponents (52, 54) which are orientated so that the commutation blocksupports only a positive voltage or zero voltage.
 14. Device accordingto claim 12, characterised in that the inhibiting means (13) aresuitable for supplying the inhibiting signal when the potentialdifference between the input terminal (7) and the neutral terminal (3)of the source (1) is positive, the commutation matrix (12) further beingformed by electronic components (52, 54) which are orientated so thatthe commutation block supports only a negative voltage or zero voltage.15. Device according to claim 1, characterised in that it can beconnected to at least two input alternating voltage sources (1 ₁ to 1_(n)), the neutral terminals (3 ₁ to 3 _(n)) of which are all connectedto each other and which are associated with the same number of loads (4₁ to 4 _(n)) which form output alternating current sources and outputterminals (5 ₁ to 5 _(n)) of which are also all connected to each other,and in that it comprises a plurality of commutation blocks (6 ₁ to 6_(n)), the reference terminals (9 ₁ to 9 _(n)) of the commutation blocks(6 ₁ to 6 _(n)) all being connected to each other.
 16. Device accordingto claim 15, characterised in that the neutral terminals (3 ₁ to 3 _(n))of the sources (1 ₁ to 1 _(n)) are accessible in order to allow aconnection, and in that it comprises a shift block (14) which comprisesan input terminal (15) which is suitable for being connected to theneutral terminals (3 ₁ to 3 _(n)), a reference terminal (16) which isconnected to all of the reference terminals (9 ₁ to 9 _(n)) of thecommutation blocks (6 ₁ to 6 _(n)) and an output terminal (17) which canbe connected to all of the output terminals (5 ₁ to 5 _(n)) of the loads(4 ₁ to 4 _(n)) which form an output alternating current source, theshift block (14) allowing the potential of the output terminal (17),which can be connected to the output terminals (5 ₁ to 5 _(n)) of theloads (4 ₁ to 4 _(n)), to be modified.
 17. Device according to claim 15,characterised in that the means for permanent maintenance, at a constantsign or zero, of the potential difference between the input terminal (7₁ to 7 _(n)) and the reference terminal (9 ₁ to 9 _(n)) compriseinhibiting means (13 ₁ to 13 _(n)) which are associated with the or eachcommutation block (6 ₁ to 6 _(n)) and which comprise means for comparingthe potential difference between the input terminals (7 ₁ to 7 _(n)) anda terminal having a potential common to all of the commutation blocks (6₁ to 6 _(n)), such as the neutral terminals (3 ₁ to 3 _(n)) of thesources (1 ₁ to 1 _(n)), the output terminals (5 ₁ to 5 _(n)) of theloads (4 ₁ to 4 _(n)) or the reference terminals (9 ₁ to 9 _(n)), whichmeans are suitable for supplying at the output signals for inhibitingthe commutation blocks (6 ₁ to 6 _(n)), and in that the or eachcommutation block (6 ₁ to 6 _(n)) is suitable for connecting togetherthe input terminal (7 ₁ to 7 _(n)), the reference terminal (9 ₁ to 9_(n)) and the output terminal (10 ₁ to 10 _(n)) thereof when theinhibiting signal is received.
 18. Device according to claim 17,characterised in that the inhibiting means (13 ₁ to 13 _(n)) aresuitable for supplying an inhibiting signal only to the block whosepotential difference between the input terminals (7 ₁ to 7 _(n)) and aterminal having a potential common to all of the commutation blocks (6 ₁to 6 _(n)), such as the neutral terminals (3 ₁ to 3 _(n)) of the sources(1 ₁ to 1 _(n)), the output terminals (5 ₁ to 5 _(n)) of the loads (4 ₁to 4 _(n)) or the reference terminals (9 ₁ to 9 _(n)), is the weakest,the commutation matrices (12 ₁ to 12 _(n)) further being formed byelectronic components (52, 54) which are orientated so that the blocks(6 ₁ to 6 _(n)) support only a positive voltage or zero voltage. 19.Device according to claim 18, characterised in that the inhibiting means(13 ₁ to 13 _(n)) are suitable for supplying an inhibiting signal onlyto the block whose potential difference between the input terminals (7 ₁to 7 _(n)) and a terminal having a potential common to all of thecommutation blocks (6 ₁ to 6 _(n)), such as the neutral terminals (3 ₁to 3 _(n)) of the sources (1 ₁ to 1 _(n)), the output terminals (5 ₁ to5 _(n)) of the loads (4 ₁ to 4 _(n)) or the reference terminals (9 ₁ to9 _(n)), is the greatest, the commutation matrices (12 ₁ to 12 _(n))further being formed by electronic components (52, 54) which areorientated so that the blocks (6 ₁ to 6 _(n)) support only a negativevoltage or zero voltage.
 20. Device according to claim 1, characterisedin that it is suitable for being connected to three input alternatingvoltage sources (1 ₁ to 1 ₃) which form the three phases of athree-phase electrical energy supply network.
 21. Device according toclaim 20, characterised in that each matrix (12 ₁, 12 ₂ and 12 ₃) ofeach commutation block (6 ₁, 6 ₂, 6 ₃) comprises a single capacitor (20_(j,i,k)) and a single commutation cell (2 _(j,i,k)).